Conventionally, a semiconductor device in which a semiconductor chip is mounted on an insulating base material is well known. As the method of mounting a semiconductor chip on an insulating base material and electrically connecting the semiconductor chip to an electrode pad formed on the insulating base material surface, the wire bonding method is widely used.
The wire connection method based on wire bonding is a method, as shown in FIG. 6, of mutually connecting a bonding pad 22a formed on an upper surface of a semiconductor chip 22 and an electrode pad 11a on the side of an insulating base material 11 via a wire 13 formed from gold, copper or the like and having a diameter of several 10 μm. More specifically, this is a method of connecting a wire protruding from the tip of a capillary through a through-hole formed at the center of a movable capillary to one pad with the ultrasonic combination thermocompression bonding method, and thereafter moving the capillary to the other pad while pulling the wire out from the through hole, and connecting the wire to the pad with the ultrasonic combination thermocompression bonding method while pressing the wire and the capillary against the other pad, and simultaneously breaking the wire.
According to the wire bonding method, as shown in FIG. 6, the bonding pad 22a formed on the surface of the semiconductor chip 22 and the electrode pad 11a on the surface of the insulating base material 11 are mutually wire-connected with the wire having a diameter of roughly several 10 μm. This kind of method entails the following problems.
Under normal circumstances, in the production process of a semiconductor device, after the wire bonding process, the surface of the semiconductor chip is sealed with a seal material in order to protect the semiconductor chip, and then packaged. The seal material that is used in the foregoing sealing step usually contains large amounts of inorganic filling material so as to provide sufficient insulation or to increase the dimensional stability. Thus, the seal material containing large amounts of inorganic filling material as described above has extremely inferior fluidity. Consequently, after inserting a base material mounted with a semiconductor chip into a mold and thereafter filling the seal material inside the mold, it is necessary to perform the molding at an extremely high pressure. In such case, considerably external force is applied to the wire used for the bonding, and there was a problem in that the reliability of the semiconductor device would be impaired due to the breakage or damage of the wire. In order to resolve this kind of problem, measures of increasing the wire diameter are also being adopted. Nevertheless, expensive gold is often used as the wire. Thus, increasing the wire diameter means increased costs. In addition, with the wire bonding method, since the wire spacing cannot be narrowed in consideration of the sweep amount of the wire, there is a problem in that the wiring density is low.
As an alternative method to the wire bonding, for example, the method described in following Non-Patent Document 1 is known. The outline is specifically explained. (1) Foremost, a semiconductor chip that is fixed on a flexible substrate is coated with a silicon oxide film. Subsequently, an organic film for flattening the silicon oxide film surface is formed. Subsequently, a metal mask is used to remove the silicon oxide film on the surface of the bonding pad of the semiconductor chip surface and the surface of the electrode pad formed on the flexible substrate, and the organic film. (2) Subsequently, only the organic film of the other portions is removed. (3) Subsequently, plating seeds are attached to the entire surface, and a resist for plating is additionally formed so as to cover the plating seeds. Subsequently, a silicon oxide film is additionally formed on the surface of the resist for plating. Subsequently, an organic film for flattening the silicon oxide film surface is formed once again. (4) Subsequently, a metal mask is used to remove the silicon oxide film and the organic film along a path of the portion connecting the bonding pad and the electrode pad where the wiring should be formed. (5) Subsequently, with the silicon oxide film as the mask, the plating seeds are exposed by removing the resist for plating of the portions where the silicon oxide film is not formed. (6) Finally, by performing plating processing, plating is formed only at the portion where the plating seeds remain based on the foregoing steps, and a wiring is thereby formed.
There is also known another conventional technique of using a CMP method (Chemical Mechanical Polishing method) to form a circuit board embedded with a circuit layer comprising a conductor (e.g., Patent Document 1).
In the CMP method, first a surface of an insulating base material is laser-machined to form a circuit groove (trench portion). Next, an electroless plating coating is formed over the entire surface of the insulating base material including this circuit groove. Then, a voltage is applied to this electroless plating coating to form an electrolytic plating coating on the entire surface of the insulating base material. Thereafter, sections of the electrolytic plating coating and the electroless plating coating that are present above the insulating base material are polished and removed using a polisher, to expose the surface of the insulating base material.
Especially if the insulating base material contains a filler, the filler would be exposed on the surface of the insulating base material and destroyed as a result of the polishing process mentioned above. Consequently, the filler on the surface would not be able to keep its original shape. When the filler is exposed, particles thereof would be likely to spread and cause contamination in the subsequent steps. Moreover, as a result of polishing the surface of the insulating base material, microcracks could form from the filler exposed on the surface. The destroyed filler that is exposed on the surface of the insulating base material is likely to deteriorate the characteristics of the base material, such as its thermal expandability and strength.    Non-Patent Document 1: Reference handout of MEMS-Semiconductor Lateral Wiring Technique (Lecture of Mr. Mitsumasa Koyanagi, Professor of Tohoku University, Graduate School of Engineering) in Co-Hosted Program of 19th Micromachine/MEMS Exhibition of Fine MEMS Project Interim Result Presentation (Jul. 31, 2008 at Tokyo Big Site)    Patent Document 1: Japanese Patent Application Publication No. 2000-49162